Video decoder dynamic memory allocation system and method with error recovery
US5926227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1997 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Jul 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/70
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video decoder which uses a dynamic memory allocation scheme having a synchronization counter for decoder-display synchronization. The synchronization counter advantageously allows for graceful recovery from error conditions in which the decoding portion of the video decoder falls behind the display portion of the video decoder. In one embodiment, the video decoder includes an MPEG bitstream decoder, FIFO buffer logic, a free segment register, and a display processor. The video decoder decodes an encoded bitstream to obtain image data for storage in an external memory, and the display processor retrieves the image data for display on a monitor. To conserve memory, the bitstream decoder stores only anchor frames as complete images in the external memory, and bi-directional images are stored in dynamically allocated memory segments. Free memory segments are determined by examination of a free segment register, and pointers to the memory segments having image data are passed to the display processor via the FIFO buffers. A synchronization counter tracks the number of memory segments by which the bitstream decoder is ahead of the display processor. By monitoring the contents of the sy…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.