Silicon layer arrangement for last mask programmability
US5926419A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1997 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Jul 15, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an application specific integrated circuit (ASIC) from a multitude of silicon layers, including upper silicon layers and lower silicon layers. A processor for performing defined calculations and a random access memory (RAM) for storing a plurality of variable data values are formed in the lower layers of the application specific integrated circuit. A read only memory (ROM) is formed in the uppermost layer of the application specific integrated circuit using a metal mask. The plurality of control functions and constant data values stored in the read only memory are required for operation of a particular type of battery with a particular type of battery chemistry, such as a rechargeable nickel metal hydride battery, or a rechargeable lithium ion battery. The invention allows one core ASIC to be programmed into several separate final products, each with a different last mask ROM code layer. The method allows a wafer lot to be processed up to the last mask, and then one of several finishing options can be selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.