Semiconductor storage device having a hierarchical bit line structure
US5926432A · kind A · utility
3Cited by
4References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 28, 1998 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Jan 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Word lines are driven by respective word line driving circuits in a row selector. Bank selection line driving circuits for driving respective bank selection lines of memory cell arrays are arranged on one side of the first memory cell array and between the adjacent memory cell arrays. The bank selection line driving circuits corresponding to the respective memory cell arrays are connected in series from a row selector side. The bank selection line driving circuits drive the bank selection lines of the corresponding memory cell arrays respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.