Serial data bus and use thereof
US5928344A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/4135
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial data bus with a two-wire line and a plurality of bus nodes for the exchange of data messages in both directions between the bus nodes and a central unit connected to the bus and for the current supply of the bus nodes. Conflicts between data messages that appear simultaneously are resolved on the basis of the priority thereof. The bus is constructed in the manner of a multi-master system in which each bus and the central unit is a master, and the central unit provides the bus timing and controls the synchronization of the bus. Each bit transmission is divided up into a positive and a negative phase, the current supply of the bus nodes being effected in the positive phase and the data transmission being effected in the negative phase. The bus is preferably used for a hazard-detection system wherein the bus nodes comprise a micro-controller and either are constituted by special detectors with integrated bus or comprise an interface for the connection of the detectors. Bus protocol and bus timing are coordinated with the micro-controllers in such a way that the latter can take over the operation of the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.