Method and apparatus for verifying erasure of memory blocks within a non-volatile memory structure
US5928370A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Feb 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a digital system having non-volatile memory devices for storage of digital information therein, the digital information being organized in sectors, each sector having a data field and a corresponding extension field, a controller device for performing operations such as reading and writing to and erasing information from a selected plurality of sectors and further verifying successful erasure of the selected erased sectors, the controller device including an error detection circuit for detecting errors within each of the sector data fields using the corresponding sector extension field and a flash interface circuit coupled to the non-volatile devices through a data bus for receiving an erased sector of information therethrough and being operative to pass the data field of the erased sector information and a predetermined extension field to the error detection circuit wherein the error detection circuit calculates an extension field corresponding to the erased sector data field, compares the calculated extension field to the predetermined extension field and upon the calculated extension field not matching the predetermined extension field, detects an error in the erased sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.