Self-calibrating reversible pipeline analog to digital and digital to analog converter
US5929796A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Apr 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/72
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-calibrating reversible pipeline analog to digital converting architecture configured to convert an input analog signal to an output digital signal and further to convert an input digital signal to an output analog signal is disclosed. The reversible pipeline architecture self-calibrates to compensate for adverse effects upon the linearity during signal conversion using a digital correction procedure. The same digital correction coefficients are used during both analog to digital conversion as well as during digital to analog conversion. The self-calibrating reversible converting architecture includes a reduced gain stage to create the necessary redundancy for the digital correction. Furthermore, the self-calibrating reversible converting architecture includes an overflow reduction stage to generate redundancy for the digital correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.