Semiconductor memory device
US5930195A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1998 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Oct 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of main bit lines; a first bank having a plurality of memory cells, a plurality of word lines and a plurality of sub-bit lines; a second bank having a plurality of memory cells, a plurality of word lines and a plurality of sub-bit lines; an auxiliary conductive region connected to one of the plurality of main bit lines, the auxiliary conductive region being shared by the first bank and the second bank; a first bank selection transistor for selectively connecting one of the plurality of sub-bit lines of the first bank to the auxiliary conductive region; a second bank selection transistor for selectively connecting one of the plurality of sub-bit lines of the second bank to the auxiliary conductive region; and a first bank selection line shared by the first bank selection transistor and the second bank selection transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.