Method and apparatus for an improved code optimizer for pipelined computers
US5930510A · kind A · utility
37Cited by
11References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, methods, systems and computer program products are disclosed to provide improved optimizations of single-basic-block-loops. These optimizations include improved scheduling of blocking instructions for pipelined computers and improved scheduling and allocation of resources (such as registers) that cannot be spilled to memory. Scheduling of blocking instructions is improved by pre-allocating space in the scheduling reservation table. Improved scheduling and allocation of non-spillable resources results from converting the resource constraint into a data dependency constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.