Method of fabricating direct-bonded semiconductor wafers
US5932048A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C. in the period between the bonding step and the annealing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.