Flexible cell for gate array
US5932900A · kind A · utility
13Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
The invention provides an improvement in a cell structure for gate arrays. By using the cell in gate arrays, the design flexibility and the symmetry feature of the gate array can be retained. By providing transistors of different sizes, the design can possess more flexibility and more efficiency. Moreover, a denser chip layout can be completed. Thus, average wire lengths used for interconnections in the chip design may be shorter than previously possible. Also, better utilization of available chip area can be made. Thus, it becomes possible to flexibly and optimally use every area of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.