ESD protection clamp for mixed voltage I/O stages using NMOS transistors

US5932918A · kind A · utility

Assignee

• Digital Equipment Corporation · US

Inventor

• David Benjamin Krakauer · Cambridge, US

Key dates

• Filing date: May 4, 1998
• Grant date: Aug 3, 1999
• Expiry date: May 4, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least one pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to an I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The protection device also includes a second NMOS transistor, merged into the same active area as the first transistor, having a gate region and source region coupled to the ground plane of the mixed voltage integrated circuit. The drain region of the second transistor and the source region of the first transistor is constructed by a shared NMOS diffusion region. This shared diffusion region also constructs the common node coupling the source region of the first transistor to the drain region of the second. The shared diffusion area is a further benefit of the invention because its length controls the trigger voltage and the holding voltage of each cascode configured transistor pair. This electrostatic discharge protection device can be used either …