Self-tuning clock recovery phase-locked loop circuit
US5933058A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1996 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Nov 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.