Semiconductor device with a metal layer for supplying a predetermined potential to a memory cell section
US5933364A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1999 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Jan 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to the present invention includes: a semiconductor chip; and memory and logic sections formed on the semiconductor chip. The memory section includes: an array of memory cells; a sense amplifier circuit; and memory interconnects respectively provided in a number n (where n is a positive integer) of interconnect layers. The logic section includes logic circuits having logic interconnects respectively provided in a number n+m (where m is a positive integer) of interconnect layers. A metal layer is formed in one of (n+1)th to (n+m)th interconnect layers, covers the array of memory cells and supplies a predetermined potential to the memory section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.