Main amplifier with fast output disablement
US5933375A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Sep 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An amplifier of a type having complementary output nodes in a data output mode of operation. When an external output enable signal is at a low level, the amplifier is enabled to output a data signal. When the output enable signal is set into a high level, the amplifier is brought into an output disable mode, in which both of its output nodes are set to a low level. The amplifier contains logic circuitry for supplying the output nodes with the data signal and output enable signal. In the output disable mode, a shunting circuit is arranged between the output nodes to provide two discharge paths for a charge stored at one of the output nodes when the signal at this output node transfers from a high level to a low level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.