Method to control jitter in high-speed packet-switched networks
US5933414A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1996 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Oct 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5652
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention addresses the issue of controlling delay variations (jitter) in packet-switched networks by enhancing the capabilities of existing scheduling policies. The idea is to use a few bits in the header of packets to send jitter control information to the downstream network elements, so that the delay variation caused by the upstream network element, is compensated for by the downstream network element. The key point to observe is that packets (or cells in ATM) may be small, and therefore, not contain many bits in the header that can be used for jitter control. We describe a unique scheme, that utilizes the bits that are available for jitter control in an efficient manner, allowing for the desired jitter to be obtained with as few bits as possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.