Multiple bus system bus arbitration according to type of transaction requested and the availability status of the data buffer between the buses
US5933616A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Jul 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is provided wherein a bus master generates a signal indicative of the type of cycle it plans to initiate when requesting bus ownership. Other bus masters may be configured to generate similar cycle-type signals. A bus arbiter samples each master's unique cycle type signal during the request phase, and further receives information regarding the status of various target resources. Based upon the cycle type signals from requesting masters and upon the target resource information, the bus arbiter determines whether a master is planning to access an unavailable target resource. A master that is planning to access an unavailable target resource will be denied access of the bus. Accordingly, other masters intending to initiate cycles to available target resources may be granted ownership of the bus. As a result, target termination retry cycles may be avoided, and bus bandwidth and overall system performance may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.