Process for manufacturing discrete electronic devices

US5933715A · kind A · utility

Assignee

• Micronas Intermetall GmbH · DE

Inventors

• Gunter Igel · Teningen, DE
• Ruediger Joachim Stroh · Glückstadt, DE

Key dates

• Filing date: Mar 7, 1997
• Grant date: Aug 3, 1999
• Expiry date: Mar 7, 2017

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/978
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for manufacturing discrete electronic devices with active structures in an SOI (silicon-on-insulator) substrate which is thickened by an epitaxial layer and whose surface has a <100> orientation, said process comprising the steps of: anisotropically etching the first silicon layer to form a moat having a diameter tapering in the direction of the insulator layer, said moat extending to the insulator layer; forming an insulating layer on the sidewalls of the moat; removing a portion of the insulator layer adjoining the moat to expose a portion of the second silicon layer, which is separated from the first silicon layer by the insulator layer; forming the active structure in the second silicon layer below the portion of the insulator layer which was removed; and depositing a contact layer on the insulating layer and the active element for making contact to the active structure.