Write through virtual cache memory, alias addressing, and cache flushes
US5933844A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1994 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Apr 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are alias address to each other, a cache memory controller comprising a cache control logic, a cache tag array, a memory management unit, and an alias detection logic is provided. The cache control logic skips flushing of a cache line if the cache line is corresponding to a memory block in a non-cacheable physical memory page, thereby avoiding unnecessary flushes and allowing the CPU to update the cache memory and the main memory using an improved write through and no write allocate approach that reduces cache flushes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.