Computer implemented method for transferring packed data between register files and memory
US5935240A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for transferring packed data including the steps of first receiving an instruction from a set of instructions for transferring packed data between an extended register file and either an integer register file or a memory. In one embodiment, the extended register file includes eight registers, with each of the extended register storing up to sixty-four data bits. The integer register file also includes eight registers. The instruction includes an opcode that specifies a direction of the transfer with respect to the extended register file. The instructions are encoded in an instruction format having up to three bits addressing a destination operand and up to three bits addressing a source operand. The instruction is then translated to determine a direction of the transfer, a size of said packed data to be transferred, the address of the destination operand, and the address of the source operand. The instruction decoded by a decoder unit previously designed to decode the instruction format used to encode the set of instructions. In response to receiving the instruction, the packed data is transferred between the extended register file and either the integer register file or t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.