Skew-reduction circuit and semiconductor device
US5935257A · kind A · utility
78Cited by
3References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 30, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Oct 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for reducing skews includes a clock switching unit, receiving a clock signal, which outputs the clock signal in a first mode, and outputs a delayed clock signal obtained by delaying the clock signal in a second mode. The circuit further includes a skew reducing unit, receiving an input signal, which adjusts a phase of the input signal based on the clock signal from the clock switching unit in the first mode, and latches the input signal having an adjusted phase by using the delayed clock signal from the clock switching unit in the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.