Interface circuit and method for transmitting binary logic signals with reduced power dissipation
US5936429A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Mar 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interface circuit and method for transmitting a binary logic signal from a first electronic circuit to a second electronic circuit over a transmission line coupled to said first electronic circuit by a first terminal and to said second electronic circuit by a second terminal. The interface circuit transmits the binary logic signal by transmitting a pulse at a first potential at each falling transition of the binary logic signal, and a pulse at a second potential at each rising transition of the binary logic signal. At other times, the output terminal of a driver circuit is placed in a high-impedance state. A receiver circuit outputs a first logic Level upon receiving a pulse at the first potential, and outputs a second logic level upon receiving a pulse at the second potential. Output of these logic levels is maintained until the next pulse is received. The transmission line is preferably terminated at a potential intermediate between the first and second potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.