Zero power power-on reset circuit
US5936444A · kind A · utility
15Cited by
7References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.