Microbuffer used in synchronization of image data
US5936677A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Sep 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/440263
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
For use in a set-top box, a relatively small line buffer and a frequency control permit scaling of a video input signal and synchronization between the input signal and a composite output signal. Image data and timing signals derived from the video signal are applied to a video capture engine (VCE). When scaling the input video, the VCE combines an appropriate number of successive lines of the field being processed to produce scaled scan line data for use by a dynamic composition engine (DCE) in producing the composite image. A video odd timing signal is applied to an input odd register, which is monitored by a central processing unit (CPU). The CPU controls the values in a frequency register and in an output odd register. The value in the frequency register determines the frequency of an output clock. The signal from the output clock is applied to a horizontal timing logic circuit that produces an output horizontal sync signal. By adjusting the values in the frequency register and in the output odd register, the CPU is able to control synchronization of the composite image and to determine whether the scaled video is rapidly synchronized with the input signal or is allowed to sync…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.