Programmable logic arrays
US5936879A · kind A · utility
41Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Jul 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programming or function-setting cell for a field programmable gate array utilizes ferroelectric capacitors connected to the nodes of a latch circuit to retain charge representing the state of the cell so that, following a power loss or a specific event upset, the programming information held by the latch circuit may be reinstated. The latch circuit comprises a pair of inverters having their inputs and outputs cross-coupled by way of respective switching transistors, and the capacitors are connected between the nodes and a common plate conductor normally held at a potential intermediate the supply potentials for the inverters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.