Multiple writes per a single erase for a nonvolatile memory
US5936884A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing multiple writes before erasing a memory cell is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2.sup.m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2.sup.m adjacent levels of the memory cell. An m bit value is then read by sensing the group of 2.sup.m adjacent levels identified by the group indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.