Semiconductor memory device having reduced variation of erasing and writing voltages supplied to each memory array
US5936886A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Oct 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device comprising a plurality of memory arrays, the memory array is given a predetermined potential from a terminal via a reference line. Further, a plurality of source switches are connected to the memory arrays and the reference line. The source switches selectively transfer the predetermined potential to each of the memory arrays. In this case, each of the source switches includes a transistor having an electrical ability which is determined by a length of the reference line between each source switch and the terminal. When the transistor is formed by a MOS transistor, the above electrical ability is specified by the ON resistance of the MOS transistor. The MOS transistors are designed so that the ON resistance becomes lower as the length of the reference line between the source switch and the terminal becomes longer. At any rate, a substantially constant voltage is supplied to each of the memory arrays irrelevant of the length of the reference line between each source switch and the terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.