Method for configuring an intelligent low power serial bus
US5938742A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4256
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. A method for configuring the bus includes detecting connection and disconnection of a peripheral device to the bus. In the method, a last peripheral device on the bus is assigned the second status and all other peripheral devices on the bus are assigned the first status. Each peripheral device assigned the first status is configured to pass therethrough an interrupt signal on the bus. The last peripheral device is configured to invert an interrupt signal on the bus from a peripheral device that is newly attached to the bus. A peripheral device newly connected to the bus generates an interrupt signal that is inverted by the last peripheral device and transmitted over the bus to a host computer for the bus. Also, an interrupt signal is driven on the bus by one peripheral device on the bus upon disconnection of another peripheral device on the bus where the another peripheral device…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.