Method for managing multiple DMA queues by a single controller
US5938744A · kind A · utility
7Cited by
11References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Nov 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus whereby a single engine can manage multiple DMA queues and related functions for a mass storage subsystem such as a RAID array. By operating the engine at a suitably high clock rate, the key buses may be time multiplexed such that each bus operates at substantially its optimum frequency to maintain high efficiency of data throughput. To improve performance further, the DMA addressing function is allocated additional phases whenever the remaining buses have not requested access to the RAID engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.