Hardware command block delivery queue for host adapters and other devices with onboard processors
US5938747A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Mar 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for queuing hardware control blocks, such as SCBs, for a system including a system processor coupled to a plurality of host adapter devices and a buffer memory controller device by an I/O bus is based on use of an endless new hardware command block queue, and an endless done hardware command block queue. The hardware command blocks for a plurality of devices, where each device includes a device processor, are managed by forming an endless queue for a device in a memory external to the device. A first pointer to the endless queue is maintained in a memory that is not within the memory space of the device processor. A second pointer to the endless queue is maintained in a memory addressable by the device processor. The first and second pointers address the head and tail hardware command block array sites of the endless queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.