Bottom lead semiconductor chip stack package
US5939779A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | May 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bottom lead semiconductor chip stack package which includes a first body and a second body. The first body includes a pair of lead frames, each lead frame having a first lead portion and a second lead portion. A protrusion enclosed in a solder extends from the first lead portion. The first body also includes a semiconductor chip containing chip pads disposed on the surface thereof, the chip pads being connected to the solder enclosed protrusions. The second body has substantially the same structural configurations as the first body and is reversely stacked relative to the first body such that the semiconductor chips are disposed in opposing relationship relative to each other. An adhesive attaches the lead frames of the first body to the corresponding lead frames of the second body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.