Programmed memory with improved speed and power consumption
US5940332A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Nov 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array that has a plurality of memory cells arranged in rows and columns for storing the reorganized array. The memory also has a plurality of flag memory cells and a row of XOR gates and inverters. The initial array is divided into sections. Each row of each section of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. Each column of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. This is repeated until each row in each section and each column has at least as many ones as zeros, producing the reorganized array. The reorganized array is stored in the data circuit array, and the flag bits corresponding to each row of each section are stored in the flag memory cells. Each XOR gate is connected to one column of the memory cells and to the column of the flag memory cells that correspond to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.