Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register
US5940345A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combinational logic feedback circuit ensures correct power-on-reset of a 4-bit synchronous shift register used to generate a plurality of page select signals. The combinational circuit monitors the plurality of page select signals and asserts an invalidity signal when an invalid state is detected. A deglitch circuit inhibits or suppresses glitches which may be output from the combinational circuit due to state transitions of one or more of the page select signals. The deglitch circuit generates in response thereto a reset signal which is applied to the synchronous shift register to reset the shift register to output a valid state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.