Method for production of semiconductor integrated circuit device
US5940708A · kind A · utility
5Cited by
10References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1996 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Jul 31, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
A method for the production of a semiconductor integrated circuit device is disclosed, wherein the formation of lateral wall spacers for high voltage MOS transistor is implemented by forming a resist film for covering at least an insulating film formed on a drain region of low impurity concentration in the proximity of a gate electrode, masking the resist film, and etching the parts of the insulating film destined to give rise to the lateral wall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.