Instruction cache memory apparatus with advanced read function that predicts whether to read out a next instruction block including an address register, a counter and a selector
US5940857A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1997 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Aug 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction cache memory provides a low probability of occurrence of cache error. The instruction cache memory includes an advance read function with an instruction cache for providing/receiving instruction formation in block unit to/from a main memory, an instruction analysis section for predicting whether it is necessary to read out a next block from the main memory by analyzing the instructions included in the block read out from the main memory presently being transferred to the instruction cache, and circuits for reading out the next block from the main memory to transfer to the instruction cache when predicted to be necessary by the instruction analysis section. Prediction is done by judging if a branch predict signal produced within the instruction cache memory is present or not, judging the branch destination to be within the block or in the next block when the branch instruction is detected, and judging whether the branch operation is a forward branch or a backward branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.