Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains
US5940860A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Aug 17, 1999 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common protocol and irrespective whether the external device and the common bus both operate at the same speed. Each of the memory blocks has a local physical address at a memory module of the computer node and an associated memory tag (Mtag) for tracking a state associated with that memory block, including a state for indicating whether that memory block is exclusive to the computer node, a state for indicating whether that memory block is shared by the computer node with the external device, and a state for indicating whether that memory block is invalid in the computer node. The apparatus includes receiver logic configured to receive, when coupled to the common bus of the computers node, memory access requests specific to the apparatus on the common bus. There is further included a protocol transformer logic coupled to the receiver logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.