Method and apparatus using a plural level processor for controlling a data bus
US5941966A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a device and a process for the control of a data transmission channel or data bus, in particular a data bus on which the data is transmitted in a bit serial fashion according to a prescribed transmission protocol or bus protocol. The multitude of data buses which currently exist or will be developed in the future have their own proprietary data bus protocols and this means that for almost every data bus a special control device is required. The invention just described permits a multitude of data buses to be controlled by using a hierarchical processor architecture with at least two processor levels, which are respectively optimized for specific control tasks. The invention can be used for the control of a multitude of data buses, on which data is transmitted according to different transmission protocols. The invention is particularly suitable for the control of a multitude of field data buses or field buses for general applications, and in particular for the control of field buses in motor vehicles, such as ABUS, CAN bus, SAE bus J1850 or VAN bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.