High-temperature superconducting random access memory
US5942765A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Nov 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7). By use of the characteristic where the output is occurred according to the polarity of the flux quantum held by the first loop, the writing and reading of the memory is done by a binary logic of "0" and "1", and functions as a random access memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.