Level shift circuit formed by two cascaded CMOS inverters
US5942915A · kind A · utility
5Cited by
10References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 9, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Sep 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0289
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a level shift circuit including cascaded first and second CMOS inverters, the first CMOS inverter is powered by a first power supply voltage and a second power supply voltage lower than the first power supply voltage. Also, the second CMOS inverter is powered by the first power supply voltage and a third power supply voltage lower than the first power supply voltage. An input voltage supplied to the first CMOS inverter has a high level lower than the first power supply voltage and a low level higher than the second power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.