Method for the control of a memory cell and one-time programmable non-volatile memory using CMOS technology
US5943264A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Apr 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell in an integrated circuit using CMOS technology includes the following in series: an N type selection MOS transistor and a PN semiconductor junction. The source of the transistor is connected to the N type zone of the junction by a metal contact made on at least a part of the N type zone. The method of control includes, in the programming mode, the application to the integrated circuit of a level of supply voltage greater than a nominal value, within an upper limit that is permissible for the integrated circuit, and the application of this level to the drain and the gate of the selection transistor. The selection transistor is made with a channel having a length smaller than or equal to the minimum length in the technology considered. Accordingly, the selection transistor is biased in the snap-back mode. The memory cell may be used in a memory circuit in matrix form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.