Two-transistor DRAM cell for logic process technology
US5943270A · kind A · utility
23Cited by
2References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM cell is provided which includes a read bit line capable of being precharged to a first voltage level, a write bit line capable of carrying data, a read word line capable of being asserted at a second voltage level, and a write word line capable of being asserted at about the first voltage level. A first switching device having an enable input is coupled between the read bit line and the word read line. A second switching device having an enable input coupled to the write word line is coupled between the write bit line and the enable input of the first switching device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.