Method and apparatus for amplifying a signal to produce a latched digital signal
US5943274A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Feb 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for amplifying a signal (50) to produce a latched digital signal (46). In one embodiment, an output stage circuit (24) of memory (10) includes a differential amplifier circuit (100), a level converter (102), a timing circuit (104), a clock-free latch (106), a high impedance control circuit (108), a high impedance control circuit (110), and an output driver (112). Output stage (24) requires one clock signal to function. Alternate embodiments may skew the disabling edge of the clock to improve the speed characteristics of output stage (24). In one embodiment, signal (50) is a differential pair of signals provided from a memory bit cell array (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.