Fault tolerant memory system
US5943287A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system for storing data comprising a plurality of sets of bits. The system includes a memory section having a pair of ports and a plurality of memory banks. Each one of the memory banks has a plurality of addressable memory units. Each one of the memory units has: memory address control terminal; and data terminals. Each one of the sets of data is fed to the data terminals of a corresponding one of the memory units in each one of the memory banks. The system includes a pair of address control signal driver sections, each one fed by a corresponding one of the pair of ports. A pair of address control signals may be fed to a corresponding one of the pair of ports. A pair of port control logics is coupled a corresponding one of the ports and a corresponding one of the address control signal driver sections. Each one of the port logic sections is adapted to detect a fault in address control signals fed to the port thereof and to report such fault to the source of the first address control signals. The plurality of address control signal driver sections is coupled to a common bus for carrying address control signals to the plurality of driver sections. Each one of the driver sec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.