Digital signal clock recovery
US5943378A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1996 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Aug 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit for recovering a symbol clock (226) includes a level decoder (210) for determining one of a plurality of received states of a demodulated signal (105) during each symbol period of the symbol clock (226). Each of the plurality of received states corresponds to one of at least two modulation levels. The level decoder (210) generates for each of the plurality of received states a sign signal (212) having transitions at central threshold transition times and a magnitude signal (211). An edge selector (220) determines selected central threshold transition times. A synchronizable clock (225) is synchronized by the selected central threshold transition times, resulting in a significant reduction of symbol clock (226) jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.