Method for testing and for generating a mapping for an electronic device
US5943485A · kind A · utility
1Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1996 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Oct 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.