Method of fabricating 3D multilayer semiconductor circuits
US5943574A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Feb 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.