Method for manufacturing a semiconductor device having a triple-well structure
US5943595A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1998 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Feb 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having a triple-well structure, includes the steps of: forming a first well layer of a second conductivity type by implanting, as a first ion implantation, impurity ions of the second conductivity type to a specific depth from the surface of a semiconductor substrate of a first conductivity type and then subjecting the semiconductor substrate to an annealing treatment; forming a second ion-implanted region by implanting, as a second ion implantation, impurity ions of the second conductivity type into an end portion of first well layer with a specific width and at a depth from the surface of the semiconductor substrate to the surface of the first well layer to surround the first well layer; forming a third ion-implanted region by implanting, as a third ion implantation, impurity ions of the first conductivity type into a portion of the semiconductor substrate surrounded by the first well layer and the second ion-implanted region and at depth from the surface of the semiconductor surface to the surface of the first well layer; forming a second well layer and a third well layer by an annealing treatment of the second ion-implanted regio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.