Method and apparatus for reducing standby current in communications equipment
US5943613A · kind A · utility
43Cited by
10References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1996 |
| Grant date | Aug 24, 1999 |
| Priority date | — |
| Expiry date | Nov 7, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.