Power saving control system and method for use with serially connected electronic devices
US5944827A · kind A · utility
5Cited by
2References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Feb 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including a plurality of electronic devices connected together through a bus, which can realize reduction in power consumption while ensuring communications. When a bias voltage on an external bus is detected by a bias detecting circuit and a comparator, a bias voltage is output from a bias output terminal to the external bus enabling it. When a driver and receiver receive a PHY-SLEEP command through the external bus, the bias voltage kept output from the bias output terminal to the external bus is turned disabling it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.