Process for forming adjacent moats or holes
US5944976A · kind A · utility
1Cited by
3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 15, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jan 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A process for forming adjacent moats or holes in an electrically non-insulating substrate wherein an electrically insulating masking layer is deposited on the substrate. To form two adjacent moats or holes, the masking layer has an opening whose width is chosen so that it extends over a part of the overall width of the two moats or holes to be formed, and whose shape corresponds to the shape of the moats or holes to be formed. The surface of the masked substrate is then subjected to an anodic oxidation, with the oxidation voltage chosen to be so high that two adjacent moats or holes are formed per opening in the masking layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.