Load pole stabilized voltage regulator circuit
US5945818A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jun 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/565
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of the error amplifier and an output connected to a pass transistor that provides current to a load. A variable impedance device such as a FET transistor configured as a variable resistor is connected between the input and output of the gain stage to provide variable zero to cancel the varying pole when the output current drawn by the load fluctuates. Consequently, the disclosed voltage regulator has high stability without a significant increase in power dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.